This invention relates to a voltage controlled oscillator circuit and more particularly to a voltage controlled oscillator circuit for generating a frequency in a stable oscillation range even when a process fluctuation, or a variation in the temperature or power supply voltage occurs.
FIG. 1 shows a conventional voltage controlled oscillator circuit.
The voltage controlled oscillator circuit (VCO) includes a plurality (an odd number) of serially connected delay circuits 1-1, 1-2, . . . , 1-n. An output of the final stage delay circuit 1-n among the plurality of delay circuits 1-1, 1-2, . . . , 1-n is fed back to the first stage delay circuit 1-1 to construct a ring oscillator.
Each of the delay circuits 1-1, 1-2, . . . , 1-n includes p-channel MOS transistors Tr3, Tr4 serially connected between a power supply VDD and an output terminal, and n-channel MOS transistors Tr5, Tr6 serially connected between the output terminal and a ground node GND. The gates of the transistors Tr4, Tr5 of each of the delay circuits are supplied with an output of the preceding stage delay circuit, but the gates of the transistors Tr4, Tr5 of the first stage delay circuit 1-1 are supplied with an output of the final stage delay circuit 1-n.
The gate of the transistor Tr3 on the power supply VDD side is applied with a control voltage VPC and the gate of the transistor Tr6 on the ground node GND side is applied with a control voltage VNC. The control voltage VPC is output from the drain of a p-channel MOS transistor Tr1 having a source connected to the power supply VDD and a gate and drain connected to each other. The control voltage VNC is also applied to the gate of an n-channel MOS transistor Tr2. The source of the transistor Tr2 is connected to the ground node GND and the drain thereof is connected to the drain of the transistor Tr1.
The oscillation frequency f of the voltage controlled oscillator circuit with the above construction can be expressed as follows if the delay time of one delay circuit is set to t and the number of stages of the delay circuits is set to n. EQU f=1/(2.times.t.times.n)
The delay time of the delay circuit is determined by the control voltages VPC, VNC. That is, the amounts of currents flowing in the transistors Tr3, Tr6 are changed by the control voltages VPC, VNC so as to adjust time required for an inverter constructed by the transistors Tr4, Tr5 to charge or discharge the input capacitor of the next stage delay circuit.
Thus an electric current I flowing through a series circuit of the MOS transistors Tr1 and Tr2 and amount of electric current flowing through the MOS transistors Tr3 and Tr6 have a proportional relation and, therefore, the delay time of the delay circuit is controlled proportional to the electric current I.
The conductances of the transistors Tr1, Tr2 are determined by the control voltage VNC, the control voltage VPC is generated according to the conductances of the transistors Tr1, Tr2 and the control voltage VPC varies complementarily with respect to the control voltage VNC. For example, when the control voltage VNC becomes higher, the control voltage VPC becomes lower.
FIG. 2 shows the relation between the control voltage VNC of the voltage controlled oscillator circuit of FIG. 1 and the oscillation frequency thereof, that is, the oscillation frequency characteristic. The oscillation frequency of the voltage controlled oscillator circuit is changed according to the control voltage VNC. However, if the process fluctuation or a variation in the temperature or power supply voltage occurs, the oscillation frequency is significantly changed. Therefore, it becomes necessary to increase a margin of the oscillation gain (the variation width of the oscillation frequency/the variation width of the control voltage) of the voltage controlled oscillator circuit in order to permit the oscillation frequency range of the voltage controlled oscillator circuit to satisfy the specification under any circumstances. Further, in order to suppress a jitter (fluctuation of the oscillation frequency) of the voltage controlled oscillator circuit, it is necessary to lower the oscillation gain of the voltage controlled oscillator circuit. This is because the oscillation frequency is largely changed by noises or fluctuation of the control voltage if the oscillation gain of the voltage controlled oscillator circuit is large.
However, an oscillation gain of a wide range is required to attain a wide application range and a lowering of the oscillation gain indicates that the wide application is limited. For this reason, it is necessary to lower the oscillation gain of the normal voltage controlled oscillator circuit to the minimum permissible value while the oscillation gain for the application range is acquired.
However, the actual voltage controlled oscillator circuit is constructed to permit the oscillation frequency range to satisfy the specification under any circumstances by taking the process fluctuation or a variation in the temperature or power supply voltage into consideration. Therefore, for example, when the voltage controlled oscillator circuit is incorporated into a PLL circuit (Phase Locked Loop Circuit), the jitter characteristic will largely be influenced by the process fluctuation or a variation in the temperature or power supply voltage.